1. Field of the Invention
The present invention relates generally to image sensors and more particularly to reduction of reset spread in image sensors.
2. Description of the Related Art
Digital image capturing devices use image sensors to convert incident light energy into electrical signals. Image sensor designs include Charged Coupled Devices (CCD), Complementary Metal Oxide Silicon (CMOS) image sensors, and Digital Pixel System (DPS) sensors. An image sensor includes a two-dimensional array of light sensing elements called pixels. Each pixel in the array works with the lens system to respond to incident light within a local area of the scene, and produces an electrical signal describing the characteristics of the scene. The electrical signals that are output from the light sensing elements are converted to digital form, and the resulting digital pixel values form the raw data representing the scene. The raw data can be processed by an image processor to produce rendered digital images.
In CMOS image sensors, various problems arise as a result of reset noise in pixels. Reset noise relates to a variation in the reset level among pixels, and can cause two pixels that received identical light to nonetheless output different pixel values. In particular, the variation in reset level among pixels may make it difficult to know which portion of any given pixel signal is attributable to the reset level of the pixel. This variation of reset level occurs in all pixel designs such as 3T, 4T, and 5T pixels and results from several sources. Major sources of reset voltage level variations include: 1) KTC noise (AKA KT/C noise) which is caused by the random variations in the channel resistance of a reset transistor combined with the total capacitance at the source node of a reset transistor; 2) Reset charge injection which is caused by the high to low transition of a reset signal coupling through a parasitic capacitor between the gate and source of the reset transistor; 3) Process variation of transistors in the circuit, notably the turn on voltage of the reset transistor and drain to source voltage drop Vds of the source follower transistor and the reset transistor; 4) Additional parasitic capacitive coupling effects such as between the reset signal line and photodiode or metal wiring associated with the sense node which is the node connected to the reset transistor; 5) Power and signal distribution effects such as IR drop associated with the pixel voltage and control signals across large arrays; and 6) Offsets and random noise occurring in the readout circuit which processes the column signal line.
Several methods have been developed to minimize reset noise/reset spread in CMOS image sensor pixels, including changing the reset voltage dynamically, controlling the reset gate voltage in order to minimize total reset spread and/or control the reset voltage mean value, and in a 3T pixel separating the source-follower transistor's power-supply node from the reset transistor's drain and connecting the drain to the output of an amplifier and operating the reset transistor in sub-threshold region.
In addition, in 4T and 5T pixels reset noise/reset spread is often addressed by using correlated double sampling (CDS), which removes the reset level from the output pixel signals thus allowing the light-dependent portion of the signal to be obtained independent of the reset level variation. CDS techniques generally involve reading out two signals from the pixel: one signal that is read out while the pixel is being (or immediately after the pixel has been) reset (the reset signal), which indicates the reset level of the pixel, and one signal that is read out when the photodiode generated charge is being held in the floating diffusion (the light-dependent signal, pixel signal or data signal). The reset signal is then subtracted from the light dependent signal, resulting in an output signal from which the reset level is removed. The CDS operation may be performed in the analog or digital domain, or even may be accomplished concurrently with analog-to-digital conversion (such as in a single-slope ADC).